ICALEPCS2023 - List of Keywords (FPGA)

Paper	Title	Other Keywords	Page
MO2AO07	Dynamical Modelling Validation and Control Development for the New High-Dynamic Double-Crystal Monochromator (HD-DCM-Lite) for Sirius/LNLS	controls, MMI, experiment, HOM	100
	T.R. Silva Soares, J.P.S. Furtado, R.R. Geraldes, M. Saveri Silva, G.S. de Albuquerque LNLS, Campinas, Brazil
	Two new High-Dynamic Double-Crystal Monochromators (HD-DCM-Lite) are under installation in Sirius/LNLS for the new beamlines QUATI (quick-EXAFS) and SAPUCAIA (SAXS), which requires high in-position stability (5 nrad RMS in terms of pitch) whereas QUATI’s DCM demands the ability to perform quick sinusoidal scans in frequencies, for example 15 Hz at 4 mrad peak-to-peak amplitude. Therefore, this equipment aims to figure as an unparalleled bridge between slow step-scan DCMs, and channel-cut quick-EXAFS monochromators. In the previous conference, the dynamical modelling of HD-DCM-Lite was presented, indicating the expected performance to achieve QUATI and SAPUCAIA requirements. In this work, we are going to present the offline validation of the dynamical modelling, comparing to the solutions achieved for the previous version of LNLS HD-DCMs. This work also presents the hardware-based control architecture development, discussing the loop shaping technique and upgrades in the system, such as the increase of the position resolution, synchronization of the rotary stages, and FPGA code optimization. Furthermore, we describe how the motion controller was developed, given the high-performance motion control, such as complex control algorithm in parallel with a minimal jitter and the expectations for the beamlines commissioning regarding detector and undulator synchronization.
	Slides MO2AO07 [2.432 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO2AO07
About •	Received ※ 06 October 2023 — Revised ※ 07 October 2023 — Accepted ※ 12 December 2023 — Issued ※ 19 December 2023
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MO4AO02	HydRA: A System-on-Chip to Run Software in Radiation-Exposed Areas	radiation, software, electron, electronics	217
	T. Gingold, G. Daniluk, J. Serrano, T. Włostowski CERN, Meyrin, Switzerland M. Rizzi PSI, Villigen PSI, Switzerland
	In the context of the High-Luminosity LHC project at CERN, a platform has been developed to support groups needing to host electronics in radiation-exposed areas. This platform, called DI/OT, is based on a modular kit consisting of a System Board, Peripheral Boards and a radiation-tolerant power converter, all housed in a standard 3U crate. Groups customise their systems by designing Peripheral Boards and developing custom gateware and software for the System Board, featuring an IGLOO2 flash-based FPGA. It is compulsory for gateware designs to be radiation-tested in dedicated facilities before deployment. This process can be cumbersome and affects iteration time because access to radiation testing facilities is a scarce commodity. To make customisation more agile, we have developed a radiation-tolerant System-on-Chip (SoC), so that a single gateware design, extensively validated, can serve as a basis for different applications by just changing the software running in the processing unit of the SoC. HydRA (Hydra-like Resilient Architecture) features a triplicated RISC-V processor for safely running software in a radiation environment. This paper describes the overall context for the project, and then moves on to provide detailed explanations of all the design decisions for making HydRA radiation-tolerant, including the protection of programme and data memories. Test harnesses are also described, along with a summary of the test results so far. It concludes with ideas for further development and plans for deployment in the LHC. https://ohwr.org/project/hydra/wikis/home https://ohwr.org/project/diot/wikis/home
	Slides MO4AO02 [11.131 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO02
About •	Received ※ 06 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 27 October 2023
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MO4AO03	The DESY Open Source FPGA Framework	framework, simulation, hardware, embedded	222
	Ł. Butkowski, A. Bellandi, M. Büchler, B. Dursun, C. Gümüş, N. Omidsajedi, K. Schulz DESY, Hamburg, Germany
	Modern FPGA firmware development involves integrating various intellectual properties (IP), modules written in hardware description languages (HDL), high-level synthesis (HLS), and software/hardware CPUs with embedded Linux or bare-metal applications. This process may involve multiple tools from the same or different vendors, making it complex and challenging. Additionally, scientific institutions such as DESY require long-term maintenance and reproducibility for designs that may involve multiple developers, further complicating the process. To address these challenges, we have developed an open-source FPGA firmware framework (FWK) at DESY that streamlines development, facilitates collaboration, and reduces complexity. The FWK achieves this by providing an abstraction layer, a defined structure, and guidelines to create big FPGA designs with ease. FWK also generates documentation and address maps necessary for high-level software frameworks like ChimeraTK. This paper presents an overview and the idea of the FWK.
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO03
About •	Received ※ 05 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 13 October 2023
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MO4AO05	Development of a Timing and Data Link for EIC Common Hardware Platform	network, timing, alignment, site	228
	P. Bachek, T. Hayes, J. Mead, K. Mernick, G. Narayan, F. Severino BNL, Upton, New York, USA
	Funding: Contract Number DE-AC02-98CH10886 with the auspices of the US Department of Energy Modern timing distribution systems benefit from high configurability and the bidirectional transfer of timing data. The Electron Ion Collider (EIC) Common Hardware Platform (CHP) will integrate the functions of the existing RHIC Real Time Data Link (RTDL), Event Link, and Beam Sync Link, along with the Low-Level RF (LLRF) system Update Link (UL), into a common high speed serial link. One EIC CHP carrier board sup-ports up to eight external 8 Gbps high speed links via SFP+ modules, as well as up to six 8 Gbps high speed links to each of two daughterboards. A daughterboard will be designed for the purpose of timing data link distribution for use with the CHP. This daughterboard will have two high speed digital crosspoint switches and a Xilinx Artix Ultrascale⁺ FPGA onboard with GTY transceivers. One of these will be dedicated for a high-speed control and data link directly between the onboard FPGA and the carrier FPGA. The remaining GTY transceivers will be routed through the crosspoint switches. The daughterboard will support sixteen external SFP+ ports for timing distribution infrastructure with some ports dedicated for transmit only link fanout. The timing data link will support bidirectional data transfer including sending data or events from a downstream device back upstream. This flexibility will be achieved by routing the SFP+ ports through the crosspoint switches which allows the timing link datapaths to be forwarded directly through the daughterboard to the carrier and into the FPGA on the daughterboard in many different configurations.
	Slides MO4AO05 [1.236 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO05
About •	Received ※ 05 October 2023 — Revised ※ 07 October 2023 — Accepted ※ 23 November 2023 — Issued ※ 07 December 2023
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MO4AO06	Overview and Outlook of FPGA Based Hardware Solutions for Data Synchronization, Acquisition and Processing at the Euxfel	FEL, hardware, timing, framework	233
	B.J. Fernandes, F. Babies, T. Freyermuth, P. Gessler, I.S. Soekmen, H. Sotoudi Namin EuXFEL, Schenefeld, Germany
	The European X-Ray Free Electron Laser facility (EuXFEL) provides ultra short coherent X-Ray flashes, spaced by 220 nanoseconds and with a duration of less than 100 femtoseconds, in bursts of up to 2700 pulses every 100ms to several instruments. The facility has been using standardized Field-Programmable Gate Array (FPGA) based hardware platforms since the beginning of user operation in 2017. These are used for timing distribution, data processing from large 2D detectors, high speed digitizers for acquisition and processing of pulse signals, monitoring beam characteristics, and low latency communication protocol for pulse data vetoing and Machine Protection System (MPS). Our experience grows in tandem with user requests for more specific and challenging case studies, leading to tailor made hardware algorithms and setups. In some cases, these can be fulfilled with the integration of new hardware, where collaboration with companies for new and/or updated platforms is a key factor, or taking advantage of unused features in current setups. In this overview, we present the FPGA hardware based solutions used to fulfill EuXFEL’s requirements. We also present our efforts in integrating new solutions and possible development directions, including Machine Learning (ML) research, with the aim of bringing more accurate results and configurable setups to user experiments and facilitate communications with other platforms used in the facility, namely Programmable Logic Controllers (PLC).
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO06
About •	Received ※ 06 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 23 October 2023
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MO4AO07	Status of the MicroTCA Based Beam Instrumentation DAQ Systems at GSI and FAIR	timing, hardware, detector, instrumentation	239
	T. Hoffmann, H. Bräuning, R.N. Geißler, T. Milosic GSI, Darmstadt, Germany
	While the first FAIR accelerator buildings are soon to be completed, MicroTCA-based data acquisition sys-tems for FAIR beam instrumentation are ready for use. By using commercial off-the-shelf components as well as open hardware with in-house expertise in FPGA programming, there are now DAQ solutions for almost all major detector systems in MicroTCA in operation at the existing GSI accelerators. Applications span a wide range of detector systems and hardware, often taking advantage of the high channel density and data trans-mission bandwidth available with MicroTCA. All DAQ systems are synchronised and triggered using a com-prehensive White Rabbit based timing system. This allows correlation of the data from the distributed acquisition systems on a nanosecond scale. In this paper, we present some examples of our DAQ implemented in MicroTCA covering the range of beam current, tune, position and profile measurements. While the latter uses GigE cameras in combination with scintillating screens, the other applications are based on ADCs with different sampling frequencies between 125 MSa/s up to 2.5 GSa/s or latching scalers with up to 10 MHz latching frequency.
	Slides MO4AO07 [3.497 MB]
	Poster MO4AO07 [3.790 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO07
About •	Received ※ 29 September 2023 — Revised ※ 07 October 2023 — Accepted ※ 14 November 2023 — Issued ※ 07 December 2023
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TU1BCO04	Laser Focal Position Correction Using FPGA-Based ML Models	controls, laser, network, simulation	262
	J.A. Einstein-Curtis, S.J. Coleman, N.M. Cook, J.P. Edelen RadiaSoft LLC, Boulder, Colorado, USA S.K. Barber, C.E. Berger, J. van Tilborg LBNL, Berkeley, California, USA
	Funding: This material is based upon work supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics under Award Number DE-SC 00259037. High repetition-rate, ultrafast laser systems play a critical role in a host of modern scientific and industrial applications. We present a diagnostic and correction scheme for controlling and determining laser focal position by utilizing fast wavefront sensor measurements from multiple positions to train a focal position predictor. This predictor and additional control algorithms have been integrated into a unified control interface and FPGA-based controller on beamlines at the Bella facility at LBNL. An optics section is adjusted online to provide the desired correction to the focal position on millisecond timescales by determining corrections for an actuator in a telescope section along the beamline. Our initial proof-of-principle demonstrations leveraged pre-compiled data and pre-trained networks operating ex-situ from the laser system. A framework for generating a low-level hardware description of ML-based correction algorithms on FPGA hardware was coupled directly to the beamline using the AMD Xilinx Vitis AI toolchain in conjunction with deployment scripts. Lastly, we consider the use of remote computing resources, such as the Sirepo scientific framework, to actively update these correction schemes and deploy models to a production environment. M.S. Rakitin et al., "Sirepo: an open-source cloud-based software interface for X-ray source and optics simulations" Journal of Synchrotron Radiation25, 1877-1892 (Nov 2018).
	Slides TU1BCO04 [1.876 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TU1BCO04
About •	Received ※ 06 October 2023 — Accepted ※ 14 November 2023 — Issued ※ 18 December 2023
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TU1BCO06	Disentangling Beam Losses in The Fermilab Main Injector Enclosure Using Real-Time Edge AI	real-time, controls, operation, network	273
	K.J. Hazelwood, J.M.S. Arnold, M.R. Austin, J.R. Berlioz, P.M. Hanlet, M.A. Ibrahim, A.T. Livaudais-Lewis, J. Mitrevski, V.P. Nagaslaev, A. Narayanan, D.J. Nicklaus, G. Pradhan, A.L. Saewert, B.A. Schupbach, K. Seiya, R.M. Thurman-Keup, N.V. Tran Fermilab, Batavia, Illinois, USA J.YC. Hu, J. Jiang, H. Liu, S. Memik, R. Shi, A.M. Shuping, M. Thieme, C. Xu Northwestern University, EVANSTON, USA A. Narayanan Northern Illinois University, DeKalb, Illinois, USA
	The Fermilab Main Injector enclosure houses two accelerators, the Main Injector and Recycler Ring. During normal operation, high intensity proton beams exist simultaneously in both. The two accelerators share the same beam loss monitors (BLM) and monitoring system. Deciphering the origin of any of the 260 BLM readings is often difficult. The (Accelerator) Real-time Edge AI for Distributed Systems project, or READS, has developed an AI/ML model, and implemented it on fast FPGA hardware, that disentangles mixed beam losses and attributes probabilities to each BLM as to which machine(s) the loss originated from in real-time. The model inferences are then streamed to the Fermilab accelerator controls network (ACNET) where they are available for operators and experts alike to aid in tuning the machines.
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TU1BCO06
About •	Received ※ 06 October 2023 — Revised ※ 11 October 2023 — Accepted ※ 15 November 2023 — Issued ※ 06 December 2023
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TUPDP006	System Identification Embedded in a Hardware-Based Control System with CompactRIO	controls, experiment, HOM, real-time	489
	T.R. Silva Soares, J.L. Brito Neto, J.P.S. Furtado, R.R. Geraldes LNLS, Campinas, Brazil
	The development of innovative model-based design high bandwidth mechatronic systems with stringent performance specifications has become ubiquitous at LNLS-Sirius beamlines. To achieve such unprecedent specifications, closed loop control architecture must be implemented in a fast, flexible and reliable platform such as NI CompactRIO (cRIO) controller that combines FPGA and real-time capabilities. The design phase and life-cycle management of such mechatronics systems heavily depends on high quality experimental data either to enable rapid prototyping, or even to implement continuous improvement process during operation. This work aims to present and compare different techniques to stimulus signal generation approaching Schroeder phasing and Tukey windowing for better crest factor, signal-to-noise ratio, minimum mechatronic stress, and plant identification. Also show the LabVIEW implementation to enable embeddeding this framework that requires specific signal synchronization and processing on the main application containing a hardware-based control architecture, increasing system diagnostic and maintenance ability. Finally, experimental results from the High-Dynamic Double-Crystal Monochromator (HD-DCM-Lite) of QUATI (quick absorption spectroscopy) and SAPUCAIA (small-angle scattering) beamlines and from the High-Dynamic Cryogenic Sample Stage from SAPOTI (multi-analytical X-ray technique) of CARNAÚBA beamline are also presented in this paper.
	Poster TUPDP006 [0.766 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP006
About •	Received ※ 06 October 2023 — Revised ※ 08 October 2023 — Accepted ※ 09 December 2023 — Issued ※ 13 December 2023
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TUPDP050	Development and Test Operation of the Prototype of the New Beam Interlock System for Machine Protection of the RIKEN RI Beam Factory	controls, EPICS, operation, experiment	645
	M. Komiyama, M. Fujimaki, N. Fukunishi, A. Uchiyama RIKEN Nishina Center, Wako, Japan M. Hamanaka, K. Kaneko, R. Koyama, M. Nishimura, H. Yamauchi SHI Accelerator Service Ltd., Tokyo, Japan A. Kamoshida National Instruments Japan Corporation, MInato-ku, Tokyo, Japan
	We have been operating the beam interlock system (BIS) for machine protection of the RIKEN RI Beam Factory (RIBF) since 2006. It stops beams approximately 15 ms after receiving an alert signal from the accelerator and beam line components. We continue to operate BIS successfully; however, we are currently developing a successor system to stop a beam within 1 ms considering that the beam intensity of RIBF will continue to increase in the future. After comparing multiple systems, CompactRIO, a product by National Instruments, was selected for the successor system. Interlock logic for signal input/output is implemented on the field-programmable gate array (FPGA) because fast processing speed is required. On the other hand, signal condition setting and monitoring do not require the same speed as interlock logic. They are implemented on the RT-OS and controlled by using experimental physics and industrial control system (EPICS) by setting up an EPICS server on the RT-OS. As a first step in development, a prototype consisting of two stations that handle only digital alert signals was developed and installed in part of the RIBF in the summer of 2022 (224 input contacts). The signal response time of the prototype, measured with an oscilloscope, averaged 0.52 ms with both stations (the distance between two stations is approximately 75 m). Furthermore, by additionally installing a pull-up circuit at each signal input contact of the system, the system response time was successfully reduced to approximately 0.13 ms.
	Poster TUPDP050 [0.816 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP050
About •	Received ※ 03 October 2023 — Revised ※ 09 October 2023 — Accepted ※ 14 December 2023 — Issued ※ 18 December 2023
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TUPDP081	The ESS Fast Beam Interlock System - Design, Deployment and Commissioning of the Normal Conducting Linac	MMI, controls, operation, software	704
	S. Pavinato, M. Carroll, S. Gabourin, A.A. Gorzawski, A. Nordt ESS, Lund, Sweden
	The European Spallation Source (ESS) is a research facility based in Lund, Sweden. Its linac will have an high peak current of 62.5 mA and long pulse length of 2.86 ms with a repetition rate of 14 Hz. The Fast Beam Interlock System (FBIS), as core system of the Beam Interlock System at ESS, is a critical system for ensuring the safe and reliable operation of the ESS machine. It is a modular and distributed system. FBIS will collect data from all relevant accelerator and target systems through ~300 direct inputs and decides whether beam operation can start or must stop. The FBIS operates at high data speed and requires low-latency decision-making capability to avoid introducing delays and to ensure the protection of the accelerator. This is achieved through two main hardware blocks equipped with FPGA based boards: a mTCA ’Decision Logic Node’ (DLN), executing the protection logic and realizing interfaces to Higher-Level Safety, Timing and EPICS Control Systems. The second block, a cPCI form-factor ’Signal Condition Unit’ (SCU), implements the interface between FBIS inputs/outputs and DLNs. In this paper we present the implementation of the FBIS control system, the integration of different hardware and software components and a summary on its performance during the latest beam commissioning phase to DTL4 Faraday Cup in 2023.
	Poster TUPDP081 [2.284 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP081
About •	Received ※ 26 September 2023 — Accepted ※ 11 December 2023 — Issued ※ 16 December 2023
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TUPDP111	Software and Firmware-Logic Design for the PIP-II Machine Protection System Mode and Configuration Control at Fermilab	controls, interface, operation, linac	832
	L.R. Carmichael, M.R. Austin, E.R. Harms, R. Neswold, A. Prosser, A. Warner, J.Y. Wu Fermilab, Batavia, Illinois, USA
	Funding: This manuscript has been authored by Fermi Research Alliance, LLC under Contract No. DE-AC02-07CH11359 with the U.S. Department of Energy, Office of Science, Office of High Energy Physics The PIP-II Machine Protection System (MPS) requires a dedicated set of tools for configuration control and management of the machine modes and beam modes of the accelerator. The protection system reacts to signals from various elements of the machine according to rules established in a setup database filtered by the program Mode Controller. This is achieved in accordance with commands from the operator and governed by the firmware logic of the MPS. This paper describes the firmware logic, architecture, and implementation of the program mode controller in an EPICs based environment.
	Poster TUPDP111 [2.313 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP111
About •	Received ※ 03 October 2023 — Revised ※ 09 October 2023 — Accepted ※ 04 December 2023 — Issued ※ 12 December 2023
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TUPDP123	SLAC ATCA Scope - Upgrading the EPICS Support Package	EPICS, software, controls, interface	873
	D. Alnajjar, M.P. Donadio, K.H. Kim, R. Ruckman SLAC, Menlo Park, California, USA
	Funding: Work supported by US DOE contract DE-AC02-76SF00515 The SLAC ATCA Scope, a 4-channel dual scope, has an EPICS support package that runs on top of SLAC’s Common Platform software and firmware, and communicates with several high-performance systems in LCLS running on the 7-slot Advanced Telecommunications Computing Architecture (ATCA) crate. The software was completely refactored to improve the usability for IOC engineers. Once linked with an EPICS IOC, it initializes the scope hardware and instantiates the upper software stack providing a set of PVs to control the API and hardware, and to operate the oscilloscope. The exported PVs provide seamless means to configure triggers and obtain data acquisitions similar to a real oscilloscope. The ATCA scope probes are configured dynamically by the user to probe up to four inputs of the ATCA ADC daughter cards. The EPICS support package automatically manages available ATCA carrier board DRAM resources based on the number of samples requested by the user, allowing acquisitions of up to 8 GBytes per trigger. The user can also specify a desired sampling rate, and the ATCA Scope will estimate the nearest possible sampling rate using the current sampling frequency, and perform downsampling to try to match that rate. Adding the EPICS module to an IOC is simple and straightforward. The ATCA Scope support package works for all high-performance systems that have the scope common hardware implemented in its FPGAs. Generic interfaces developed in PyDM are also provided to the user to control the oscilloscope and enrich the user’s seamless overall experience.
	Poster TUPDP123 [0.984 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP123
About •	Received ※ 03 October 2023 — Accepted ※ 30 November 2023 — Issued ※ 08 December 2023
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WE1BCO01	VME2E: VME to Ethernet - Common Hardware Platform for legacy VME Module Upgrade	Ethernet, hardware, controls, real-time	949
	J.P. Jamilkowski Brookhaven National Laboratory (BNL), Electron-Ion Collider, Upton, New York, USA Y. Tian BNL, Upton, New York, USA
	Funding: DOE Office of Science VME architecture was developed in late 1970s. It has proved to be a rugged control system hardware platform for the last four decades. Today the VME hardware platform is facing four challenges from 1) backplane communication speed bottleneck; 2) computing power limits from centralized computing infrastructure; 3) obsolescence and cost issues to support a real-time operating system; 4) obsolescence issues of the legacy VME hardware. The next generation hardware platform such as ATCA and microTCA requires fundamental changes in hardware and software. It also needs large investment. For many legacy system upgrades, this approach is not applicable. We will discuss an open-source hardware platform, VME2E (VME to Ethernet), which allows the one-to-one replacement of legacy VME module without disassembling of the existing VME system. The VME2E has the VME form factor. It can be installed the existing VME chassis, but without use the VME backplane to communicate with the front-end computer and therefore solves the first three challenges listed above. The VME2E will only take advantage of two good benefits from a VME system: stable power supply which VME2E module will get from the backplane, and the cooling environment. The VME2E will have the most advanced 14nm Xilinx FPGA SOM with GigE for parallel computing and high speed communication. It has a high pin count (HPC) FPGA mezzanine connector (FMC) to benefit the IO daughter boards supply of the FMC ecosystem. The VME2E is designed as a low cost, open-source common platform for legacy VME upgrade.
	Slides WE1BCO01 [1.141 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-WE1BCO01
About •	Received ※ 06 October 2023 — Revised ※ 09 October 2023 — Accepted ※ 19 November 2023 — Issued ※ 22 November 2023
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THMBCMO22	Towards Defining a Synchronization Standard Between Beamline Components and Synchrotron Accelerators	experiment, interface, hardware, synchrotron	1242
	J.A. Avila-Abellan, X. Serra-Gallifa ALBA-CELLS, Cerdanyola del Vallès, Spain T.M. Cobb DLS, Oxfordshire, United Kingdom R. Hino ESRF, Grenoble, France O.H. Seeck DESY, Hamburg, Germany S. Zhang SOLEIL, Gif-sur-Yvette, France
	Funding: LEAPS-INNOV project has received funding from the European Union’s Horizon 2020 research and innovation program under Grant Agreement No 101004728 Standardization is a magic word in the electronics engineering jargon. Under its umbrella, it is generated the utopia of transparent integration with the rest of the parts with minimal extra effort for the software integration. But the experimental setup in a synchrotron beamline presents multiple challenges: it is highly dynamic and diverse. In the frame of LEAPS-INNOV project (*), the Task 3 of Work Package 5 aims to define a standard for synchronization in the beamline sample environment. Their partners (ALBA, DESY, DLS, ESRF and SOLEIL) have already reached a common vision of synchronization requirements. This paper first details the participants’ actual synchronization needs on their facilities. Next, the requirements foreseen for the future are outlined in terms of interfaces, time constraints and compatibility with timing systems. To conclude, we summarize the current state of the project: the hardware interfaces and the hardware platform definition. They both have been decided considering long-term availability, use of standard sub-components, and keeping the compromise between cost, development time, maintenance, reliability, flexibility and performance. This hardware architecture proposal meets the identified requirements. In the future, under the scope of LEAPS-INNOV, a demonstrator will be built, and we will work with the industry for its future commercialization.
	Slides THMBCMO22 [1.592 MB]
	Poster THMBCMO22 [0.760 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THMBCMO22
About •	Received ※ 06 October 2023 — Revised ※ 11 October 2023 — Accepted ※ 11 December 2023 — Issued ※ 19 December 2023
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THMBCMO26	FRIB Beam Power Ramp Process Checker at Chopper Monitor	diagnostics, target, controls, monitoring	1256
	Z. Li, E. Bernal, J. Hartford, M. Ikegami FRIB, East Lansing, Michigan, USA
	Funding: Work supporting the U.S. Dept. of Energy Office of Science under Cooperative Agreement DE-SC0023633 Chopper in the low energy beam line is a key ele-ment to control beam power in FRIB. As appropriate functioning of chopper is critical for machine protec-tion for FRIB, an FPGA-based chopper monitoring system was developed to monitor the beam gated pulse at logic level, deflection high voltage level, and in-duced charge/discharge current levels, and shut off beam promptly at detection of a deviation outside tolerance. Once FRIB beam power reaches a certain level, a cold start beam ramp mode in which the pulse repetition frequency and pulse width are linearly ramped up becomes required to mitigate heat shock to the target at beam restart. Chopper also needs to gen-erate a notch in every machine cycle of 10 ms that is used for beam diagnostics. To overcome the challeng-es of monitoring such a ramping process and meeting the response time requirement of shutting off beam, two types of process checkers, namely, monitoring at the pulse level and monitoring at the machine cycle level, have been implemented. A pulse look ahead algorithm to calculate the expected range of frequency dips and rises was developed, and a simplified mathe-matical model suitable for multiple ramp stages was built to calculate expected time parameters of accumu-lated pulse on time within a given machine cycle. Both will be discussed in detail in this paper, followed by simulation results with FPGA test bench and actual instrument test results with the beam ramp process.
	Slides THMBCMO26 [0.389 MB]
	Poster THMBCMO26 [3.028 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THMBCMO26
About •	Received ※ 04 October 2023 — Revised ※ 10 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 24 October 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPDP002	The Micro-Services of Cern’s Critical Current Test Benches	controls, software, operation, power-supply	1295
	C. Charrondière, A. Ballarino, C. Barth, J.F. Fleiter, P. Koziol, H. Reymond CERN, Meyrin, Switzerland O.Ø. Andreassen, T. Boutboul, S.C. Hopkins European Organization for Nuclear Research (CERN), Geneva, Switzerland
	In order to characterize the critical-current density of low temperature superconductors such as niobium¿titanium (NbTi) and niobium¿tin (Nb₃Sn) or high temperature superconductors such as magnesium-diboride MgB₂ or Rare-earth Barium Copper Oxide REBCO tapes, a wide range of custom instruments and interfaces are used. The critical current of a superconductor depends on temperature, magnetic field, current and strain, requiring high precision measurements in the nano Volt range, well-synchronized instrumentation, and the possibility to quickly adapt and replace instrumentation if needed. The micro-service based application presented in this paper allows operators to measure a variety of analog signals, such as the temperature of the cryostats and sample under test, magnetic field, current passing through the sample, voltage across the sample, pressure, helium level etc. During the run, the software protects the sample from quenching, controlling the current passed through it using high-speed field programmable gate array (FPGA) systems on Linux Real-Time (RT) based PCI eXtensions controllers (PXIe). The application records, analyzes and reports to the external Oracle database all parameters related to the test. In this paper, we describe the development of the micro-service based control system, how the interlocks and protection functionalities work, and how we had to develop a multi-windowed scalable acquisition application that could be adapted to the many changes occurring in the test facility.
	Poster THPDP002 [6.988 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP002
About •	Received ※ 06 October 2023 — Revised ※ 10 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 26 October 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPDP041	The RF Protection Interlock System Prototype Verification	LLRF, diagnostics, interface, software	1406
	W. Cichalewski, P. Amrozik, G.W. Jabłoński, W. Jalmuzna, R. Kiełbik, K. Klys, R. Kotas, P. Marciniak, B. Pekoslawski, W. Tylman TUL-DMCS, Łódż, Poland B.E. Chase, E.R. Harms, N. Patel, P. Varghese Fermilab, Batavia, Illinois, USA
	The Radio Frequency Protection Interlock system plays vital role in the LLRF related/dependent accelerator sections Protection. It’s main role is to collect information from number different sensors and indicators around nearest cavities and cryomodule and provide instant RF signal termination in case of safety thresholds violation. This submission describes newly designed RFPI system tailored to the Proton Improvement Plan II (PIP-II) requirements. The proof of concept prototype of this system has been build. The paper includes also the CMTF environment evaluation tests results and findings as an input to the next full-scope prototype design.
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP041
About •	Received ※ 06 October 2023 — Revised ※ 26 October 2023 — Accepted ※ 08 December 2023 — Issued ※ 13 December 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPDP056	Consolidation of the Power Trigger Controllers of the LHC Beam Dumping System	controls, network, software, power-supply	1439
	L. Strobino, N. Magnin, N. Voumard European Organization for Nuclear Research (CERN), Geneva, Switzerland
	The Power Trigger Controller (PTC) of the LHC Beam Dumping System (LBDS) is in charge of the control and supervision of the Power Trigger Units (PTU), which are used to trigger the conduction of the 50 High-Voltage Pulsed Generators (HVPG) of the LBDS kicker magnets. This card is integrated in an Industrial Control System (ICS) and has the double role of controlling the PTU operating mode and monitoring its status, and of supervising the LBDS triggering and re-triggering systems. As part of the LBDS consolidation during the LHC Long Shutdown 2 (LS2), a new PTC card was designed, based on a System-on-Chip (SoC) implemented in an FPGA. The FPGA contains an ARM Cortex-M3 softcore processor and all the required peripherals to communicate with onboard ADCs and DACs (3rd-party IPs or custom-made ones) as well as with an interchangeable fieldbus communication module, allowing the board to be integrated in various types of industrial control networks in view of future evolution. This new architecture is presented together with the advantages in terms of modularity and reusability for future projects.
	Poster THPDP056 [3.146 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP056
About •	Received ※ 05 October 2023 — Accepted ※ 08 December 2023 — Issued ※ 15 December 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPDP080	Gateware and Software for ALS-U Instrumentation	controls, hardware, software, timing	1536
	L.M. Russo, A. Amodio, M.J. Chin, W.E. Norum, K.S. Penney, G.J. Portmann, J.M. Weber LBNL, Berkeley, California, USA
	Funding: Work supported by the Director, Office of Science, Office of Basic Energy Sciences, of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231. The Advanced Light Source Upgrade (ALS-U) is a diffraction-limited light source upgrade project under development at the Lawrence Berkeley National Laboratory. The Instrumentation team is responsible for developing hardware, gateware, embedded software and control system integration for diagnostics projects, including Beam Position Monitor (BPM), Fast Orbit Feedback (FOFB), High Speed Digitizer (HSD), Beam Current Monitor (BCM), as well as Fast Machine Protection System (FMPS) and Timing. This paper describes the gateware and software approach to these projects, its challenges, tests and integration plans for the novel accumulation and storage rings and transfer lines.
	Poster THPDP080 [4.586 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP080
About •	Received ※ 04 October 2023 — Revised ※ 27 October 2023 — Accepted ※ 08 December 2023 — Issued ※ 15 December 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPDP087	LCLS-II Controls Software Architecture for the Wire Scan Diagnostics	controls, diagnostics, software, electron	1556
	N. Balakrishnan, J.D. Bong, A.S. Fisher, B.T. Jacobson, L. Sapozhnikov SLAC, Menlo Park, California, USA
	Funding: This work was supported by Department of Energy, Office of Basic Energy Sciences, contract DE-AC02-76SF00515 The Super Conducting (SC) Linac Coherent Light Source II (LCLS-II) facility at SLAC is capable of delivering an electron beam at a fast rate of up to 1MHz. The high-rate necessitates the processing algorithms and data exchanges with other high-rate systems to be implemented with FPGA technology. For LCLS-II, SLAC has deployed a common platform solution (hardware, firmware, software) which is used by timing, machine protection and diagnostics systems. The wire scanner diagnostic system uses this solution to acquire beam synchronous time-stamped readings, of wire scanner position and beam loss during the scan, for each individual bunch. This paper explores the software architecture and control system integration for LCLS-II wire scanners using the common platform solution.
	Poster THPDP087 [1.079 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP087
About •	Received ※ 06 October 2023 — Revised ※ 10 October 2023 — Accepted ※ 06 December 2023 — Issued ※ 09 December 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THPDP088	ATCA-Based Beam Line Data Software for SLAC’s LCLS-II Timing System	software, EPICS, Linux, network	1560
	D. Alnajjar, M.P. Donadio, K.H. Kim, M. Weaver SLAC, Menlo Park, California, USA
	Funding: Work supported by US DOE contract DE-AC02-76SF00515 Among the several acquisition services available with SLAC’s high beam rate accelerator, all of which are contemplated in the acquisition service EPICS support package, resides the new Advanced Telecommunications Computing Architecture (ATCA) Beam Line Data (BLD) service. BLD runs on top of SLAC’s common platform software and firmware, and communicates with several high-performance systems (i.e. MPS, BPM, LLRF, timing, etc.) in LCLS, running on a 7-slot ATCA crate. Once linked with an ATCA EPICS IOC and with the proper commands called in the IOC shell, it initializes the BLD FPGA logic and the upper software stack, and makes PVs available allowing the control of the BLD data acquisition rates, and the starting of the BLD data acquisition. This service permits the forwarding of acquired data to configured IP addresses and ports in the format of multicast network packets. Up to four BLD rates can be configured simultaneously, each accessible at its configured IP destination, and with a maximum rate of 1MHz. Users interested in acquiring any of the four BLD rates will need to register in the corresponding IP destination for receiving a copy of the multicast packet on their respective receiver software. BLD has allowed data to be transmitted over multicast packets for over a decade at SLAC, but always at a maximum rate of 120 Hz. The present work focuses on bringing this service to the high beam rate high-performance systems using ATCAs, allowing the reuse of many legacy in-house-developed client software infrastructures.
	Poster THPDP088 [1.060 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP088
About •	Received ※ 03 October 2023 — Accepted ※ 06 December 2023 — Issued ※ 17 December 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Other Keywords

Page

Dynamical Modelling Validation and Control Development for the New High-Dynamic Double-Crystal Monochromator (HD-DCM-Lite) for Sirius/LNLS

controls, MMI, experiment, HOM

100

T.R. Silva Soares, J.P.S. Furtado, R.R. Geraldes, M. Saveri Silva, G.S. de Albuquerque
LNLS, Campinas, Brazil

Two new High-Dynamic Double-Crystal Monochromators (HD-DCM-Lite) are under installation in Sirius/LNLS for the new beamlines QUATI (quick-EXAFS) and SAPUCAIA (SAXS), which requires high in-position stability (5 nrad RMS in terms of pitch) whereas QUATI’s DCM demands the ability to perform quick sinusoidal scans in frequencies, for example 15 Hz at 4 mrad peak-to-peak amplitude. Therefore, this equipment aims to figure as an unparalleled bridge between slow step-scan DCMs, and channel-cut quick-EXAFS monochromators. In the previous conference, the dynamical modelling of HD-DCM-Lite was presented, indicating the expected performance to achieve QUATI and SAPUCAIA requirements. In this work, we are going to present the offline validation of the dynamical modelling, comparing to the solutions achieved for the previous version of LNLS HD-DCMs. This work also presents the hardware-based control architecture development, discussing the loop shaping technique and upgrades in the system, such as the increase of the position resolution, synchronization of the rotary stages, and FPGA code optimization. Furthermore, we describe how the motion controller was developed, given the high-performance motion control, such as complex control algorithm in parallel with a minimal jitter and the expectations for the beamlines commissioning regarding detector and undulator synchronization.

Slides MO2AO07 [2.432 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO2AO07

About •

Received ※ 06 October 2023 — Revised ※ 07 October 2023 — Accepted ※ 12 December 2023 — Issued ※ 19 December 2023

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MO4AO02

HydRA: A System-on-Chip to Run Software in Radiation-Exposed Areas

radiation, software, electron, electronics

217

T. Gingold, G. Daniluk, J. Serrano, T. Włostowski
CERN, Meyrin, Switzerland
M. Rizzi
PSI, Villigen PSI, Switzerland

In the context of the High-Luminosity LHC project at CERN, a platform has been developed to support groups needing to host electronics in radiation-exposed areas. This platform, called DI/OT, is based on a modular kit consisting of a System Board, Peripheral Boards and a radiation-tolerant power converter, all housed in a standard 3U crate. Groups customise their systems by designing Peripheral Boards and developing custom gateware and software for the System Board, featuring an IGLOO2 flash-based FPGA. It is compulsory for gateware designs to be radiation-tested in dedicated facilities before deployment. This process can be cumbersome and affects iteration time because access to radiation testing facilities is a scarce commodity. To make customisation more agile, we have developed a radiation-tolerant System-on-Chip (SoC), so that a single gateware design, extensively validated, can serve as a basis for different applications by just changing the software running in the processing unit of the SoC. HydRA (Hydra-like Resilient Architecture) features a triplicated RISC-V processor for safely running software in a radiation environment. This paper describes the overall context for the project, and then moves on to provide detailed explanations of all the design decisions for making HydRA radiation-tolerant, including the protection of programme and data memories. Test harnesses are also described, along with a summary of the test results so far. It concludes with ideas for further development and plans for deployment in the LHC.
https://ohwr.org/project/hydra/wikis/home
https://ohwr.org/project/diot/wikis/home

Slides MO4AO02 [11.131 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO02

About •

Received ※ 06 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 27 October 2023

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MO4AO03

The DESY Open Source FPGA Framework

framework, simulation, hardware, embedded

222

Ł. Butkowski, A. Bellandi, M. Büchler, B. Dursun, C. Gümüş, N. Omidsajedi, K. Schulz
DESY, Hamburg, Germany

Modern FPGA firmware development involves integrating various intellectual properties (IP), modules written in hardware description languages (HDL), high-level synthesis (HLS), and software/hardware CPUs with embedded Linux or bare-metal applications. This process may involve multiple tools from the same or different vendors, making it complex and challenging. Additionally, scientific institutions such as DESY require long-term maintenance and reproducibility for designs that may involve multiple developers, further complicating the process. To address these challenges, we have developed an open-source FPGA firmware framework (FWK) at DESY that streamlines development, facilitates collaboration, and reduces complexity. The FWK achieves this by providing an abstraction layer, a defined structure, and guidelines to create big FPGA designs with ease. FWK also generates documentation and address maps necessary for high-level software frameworks like ChimeraTK. This paper presents an overview and the idea of the FWK.

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO03

About •

Received ※ 05 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 13 October 2023

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reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MO4AO05

Development of a Timing and Data Link for EIC Common Hardware Platform

network, timing, alignment, site

228

P. Bachek, T. Hayes, J. Mead, K. Mernick, G. Narayan, F. Severino
BNL, Upton, New York, USA

Funding: Contract Number DE-AC02-98CH10886 with the auspices of the US Department of Energy
Modern timing distribution systems benefit from high configurability and the bidirectional transfer of timing data. The Electron Ion Collider (EIC) Common Hardware Platform (CHP) will integrate the functions of the existing RHIC Real Time Data Link (RTDL), Event Link, and Beam Sync Link, along with the Low-Level RF (LLRF) system Update Link (UL), into a common high speed serial link. One EIC CHP carrier board sup-ports up to eight external 8 Gbps high speed links via SFP+ modules, as well as up to six 8 Gbps high speed links to each of two daughterboards. A daughterboard will be designed for the purpose of timing data link distribution for use with the CHP. This daughterboard will have two high speed digital crosspoint switches and a Xilinx Artix Ultrascale⁺ FPGA onboard with GTY transceivers. One of these will be dedicated for a high-speed control and data link directly between the onboard FPGA and the carrier FPGA. The remaining GTY transceivers will be routed through the crosspoint switches. The daughterboard will support sixteen external SFP+ ports for timing distribution infrastructure with some ports dedicated for transmit only link fanout. The timing data link will support bidirectional data transfer including sending data or events from a downstream device back upstream. This flexibility will be achieved by routing the SFP+ ports through the crosspoint switches which allows the timing link datapaths to be forwarded directly through the daughterboard to the carrier and into the FPGA on the daughterboard in many different configurations.

Slides MO4AO05 [1.236 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO05

About •

Received ※ 05 October 2023 — Revised ※ 07 October 2023 — Accepted ※ 23 November 2023 — Issued ※ 07 December 2023

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reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MO4AO06

Overview and Outlook of FPGA Based Hardware Solutions for Data Synchronization, Acquisition and Processing at the Euxfel

FEL, hardware, timing, framework

233

B.J. Fernandes, F. Babies, T. Freyermuth, P. Gessler, I.S. Soekmen, H. Sotoudi Namin
EuXFEL, Schenefeld, Germany

The European X-Ray Free Electron Laser facility (EuXFEL) provides ultra short coherent X-Ray flashes, spaced by 220 nanoseconds and with a duration of less than 100 femtoseconds, in bursts of up to 2700 pulses every 100ms to several instruments. The facility has been using standardized Field-Programmable Gate Array (FPGA) based hardware platforms since the beginning of user operation in 2017. These are used for timing distribution, data processing from large 2D detectors, high speed digitizers for acquisition and processing of pulse signals, monitoring beam characteristics, and low latency communication protocol for pulse data vetoing and Machine Protection System (MPS). Our experience grows in tandem with user requests for more specific and challenging case studies, leading to tailor made hardware algorithms and setups. In some cases, these can be fulfilled with the integration of new hardware, where collaboration with companies for new and/or updated platforms is a key factor, or taking advantage of unused features in current setups. In this overview, we present the FPGA hardware based solutions used to fulfill EuXFEL’s requirements. We also present our efforts in integrating new solutions and possible development directions, including Machine Learning (ML) research, with the aim of bringing more accurate results and configurable setups to user experiments and facilitate communications with other platforms used in the facility, namely Programmable Logic Controllers (PLC).

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO06

About •

Received ※ 06 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 23 October 2023

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reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MO4AO07

Status of the MicroTCA Based Beam Instrumentation DAQ Systems at GSI and FAIR

timing, hardware, detector, instrumentation

239

T. Hoffmann, H. Bräuning, R.N. Geißler, T. Milosic
GSI, Darmstadt, Germany

While the first FAIR accelerator buildings are soon to be completed, MicroTCA-based data acquisition sys-tems for FAIR beam instrumentation are ready for use. By using commercial off-the-shelf components as well as open hardware with in-house expertise in FPGA programming, there are now DAQ solutions for almost all major detector systems in MicroTCA in operation at the existing GSI accelerators. Applications span a wide range of detector systems and hardware, often taking advantage of the high channel density and data trans-mission bandwidth available with MicroTCA. All DAQ systems are synchronised and triggered using a com-prehensive White Rabbit based timing system. This allows correlation of the data from the distributed acquisition systems on a nanosecond scale. In this paper, we present some examples of our DAQ implemented in MicroTCA covering the range of beam current, tune, position and profile measurements. While the latter uses GigE cameras in combination with scintillating screens, the other applications are based on ADCs with different sampling frequencies between 125 MSa/s up to 2.5 GSa/s or latching scalers with up to 10 MHz latching frequency.

Slides MO4AO07 [3.497 MB]

Poster MO4AO07 [3.790 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-MO4AO07

About •

Received ※ 29 September 2023 — Revised ※ 07 October 2023 — Accepted ※ 14 November 2023 — Issued ※ 07 December 2023

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TU1BCO04

Laser Focal Position Correction Using FPGA-Based ML Models

controls, laser, network, simulation

262

J.A. Einstein-Curtis, S.J. Coleman, N.M. Cook, J.P. Edelen
RadiaSoft LLC, Boulder, Colorado, USA
S.K. Barber, C.E. Berger, J. van Tilborg
LBNL, Berkeley, California, USA

Funding: This material is based upon work supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics under Award Number DE-SC 00259037.
High repetition-rate, ultrafast laser systems play a critical role in a host of modern scientific and industrial applications. We present a diagnostic and correction scheme for controlling and determining laser focal position by utilizing fast wavefront sensor measurements from multiple positions to train a focal position predictor. This predictor and additional control algorithms have been integrated into a unified control interface and FPGA-based controller on beamlines at the Bella facility at LBNL. An optics section is adjusted online to provide the desired correction to the focal position on millisecond timescales by determining corrections for an actuator in a telescope section along the beamline. Our initial proof-of-principle demonstrations leveraged pre-compiled data and pre-trained networks operating ex-situ from the laser system. A framework for generating a low-level hardware description of ML-based correction algorithms on FPGA hardware was coupled directly to the beamline using the AMD Xilinx Vitis AI toolchain in conjunction with deployment scripts. Lastly, we consider the use of remote computing resources, such as the Sirepo scientific framework*, to actively update these correction schemes and deploy models to a production environment.
* M.S. Rakitin et al., "Sirepo: an open-source cloud-based software interface for X-ray source and optics simulations" Journal of Synchrotron Radiation25, 1877-1892 (Nov 2018).

Slides TU1BCO04 [1.876 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TU1BCO04

About •

Received ※ 06 October 2023 — Accepted ※ 14 November 2023 — Issued ※ 18 December 2023

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TU1BCO06

Disentangling Beam Losses in The Fermilab Main Injector Enclosure Using Real-Time Edge AI

real-time, controls, operation, network

273

K.J. Hazelwood, J.M.S. Arnold, M.R. Austin, J.R. Berlioz, P.M. Hanlet, M.A. Ibrahim, A.T. Livaudais-Lewis, J. Mitrevski, V.P. Nagaslaev, A. Narayanan, D.J. Nicklaus, G. Pradhan, A.L. Saewert, B.A. Schupbach, K. Seiya, R.M. Thurman-Keup, N.V. Tran
Fermilab, Batavia, Illinois, USA
J.YC. Hu, J. Jiang, H. Liu, S. Memik, R. Shi, A.M. Shuping, M. Thieme, C. Xu
Northwestern University, EVANSTON, USA
A. Narayanan
Northern Illinois University, DeKalb, Illinois, USA

The Fermilab Main Injector enclosure houses two accelerators, the Main Injector and Recycler Ring. During normal operation, high intensity proton beams exist simultaneously in both. The two accelerators share the same beam loss monitors (BLM) and monitoring system. Deciphering the origin of any of the 260 BLM readings is often difficult. The (Accelerator) Real-time Edge AI for Distributed Systems project, or READS, has developed an AI/ML model, and implemented it on fast FPGA hardware, that disentangles mixed beam losses and attributes probabilities to each BLM as to which machine(s) the loss originated from in real-time. The model inferences are then streamed to the Fermilab accelerator controls network (ACNET) where they are available for operators and experts alike to aid in tuning the machines.

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TU1BCO06

About •

Received ※ 06 October 2023 — Revised ※ 11 October 2023 — Accepted ※ 15 November 2023 — Issued ※ 06 December 2023

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TUPDP006

System Identification Embedded in a Hardware-Based Control System with CompactRIO

controls, experiment, HOM, real-time

489

T.R. Silva Soares, J.L. Brito Neto, J.P.S. Furtado, R.R. Geraldes
LNLS, Campinas, Brazil

The development of innovative model-based design high bandwidth mechatronic systems with stringent performance specifications has become ubiquitous at LNLS-Sirius beamlines. To achieve such unprecedent specifications, closed loop control architecture must be implemented in a fast, flexible and reliable platform such as NI CompactRIO (cRIO) controller that combines FPGA and real-time capabilities. The design phase and life-cycle management of such mechatronics systems heavily depends on high quality experimental data either to enable rapid prototyping, or even to implement continuous improvement process during operation. This work aims to present and compare different techniques to stimulus signal generation approaching Schroeder phasing and Tukey windowing for better crest factor, signal-to-noise ratio, minimum mechatronic stress, and plant identification. Also show the LabVIEW implementation to enable embeddeding this framework that requires specific signal synchronization and processing on the main application containing a hardware-based control architecture, increasing system diagnostic and maintenance ability. Finally, experimental results from the High-Dynamic Double-Crystal Monochromator (HD-DCM-Lite) of QUATI (quick absorption spectroscopy) and SAPUCAIA (small-angle scattering) beamlines and from the High-Dynamic Cryogenic Sample Stage from SAPOTI (multi-analytical X-ray technique) of CARNAÚBA beamline are also presented in this paper.

Poster TUPDP006 [0.766 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP006

About •

Received ※ 06 October 2023 — Revised ※ 08 October 2023 — Accepted ※ 09 December 2023 — Issued ※ 13 December 2023

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TUPDP050

Development and Test Operation of the Prototype of the New Beam Interlock System for Machine Protection of the RIKEN RI Beam Factory

controls, EPICS, operation, experiment

645

M. Komiyama, M. Fujimaki, N. Fukunishi, A. Uchiyama
RIKEN Nishina Center, Wako, Japan
M. Hamanaka, K. Kaneko, R. Koyama, M. Nishimura, H. Yamauchi
SHI Accelerator Service Ltd., Tokyo, Japan
A. Kamoshida
National Instruments Japan Corporation, MInato-ku, Tokyo, Japan

We have been operating the beam interlock system (BIS) for machine protection of the RIKEN RI Beam Factory (RIBF) since 2006. It stops beams approximately 15 ms after receiving an alert signal from the accelerator and beam line components. We continue to operate BIS successfully; however, we are currently developing a successor system to stop a beam within 1 ms considering that the beam intensity of RIBF will continue to increase in the future. After comparing multiple systems, CompactRIO, a product by National Instruments, was selected for the successor system. Interlock logic for signal input/output is implemented on the field-programmable gate array (FPGA) because fast processing speed is required. On the other hand, signal condition setting and monitoring do not require the same speed as interlock logic. They are implemented on the RT-OS and controlled by using experimental physics and industrial control system (EPICS) by setting up an EPICS server on the RT-OS. As a first step in development, a prototype consisting of two stations that handle only digital alert signals was developed and installed in part of the RIBF in the summer of 2022 (224 input contacts). The signal response time of the prototype, measured with an oscilloscope, averaged 0.52 ms with both stations (the distance between two stations is approximately 75 m). Furthermore, by additionally installing a pull-up circuit at each signal input contact of the system, the system response time was successfully reduced to approximately 0.13 ms.

Poster TUPDP050 [0.816 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP050

About •

Received ※ 03 October 2023 — Revised ※ 09 October 2023 — Accepted ※ 14 December 2023 — Issued ※ 18 December 2023

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TUPDP081

The ESS Fast Beam Interlock System - Design, Deployment and Commissioning of the Normal Conducting Linac

MMI, controls, operation, software

704

S. Pavinato, M. Carroll, S. Gabourin, A.A. Gorzawski, A. Nordt
ESS, Lund, Sweden

The European Spallation Source (ESS) is a research facility based in Lund, Sweden. Its linac will have an high peak current of 62.5 mA and long pulse length of 2.86 ms with a repetition rate of 14 Hz. The Fast Beam Interlock System (FBIS), as core system of the Beam Interlock System at ESS, is a critical system for ensuring the safe and reliable operation of the ESS machine. It is a modular and distributed system. FBIS will collect data from all relevant accelerator and target systems through ~300 direct inputs and decides whether beam operation can start or must stop. The FBIS operates at high data speed and requires low-latency decision-making capability to avoid introducing delays and to ensure the protection of the accelerator. This is achieved through two main hardware blocks equipped with FPGA based boards: a mTCA ’Decision Logic Node’ (DLN), executing the protection logic and realizing interfaces to Higher-Level Safety, Timing and EPICS Control Systems. The second block, a cPCI form-factor ’Signal Condition Unit’ (SCU), implements the interface between FBIS inputs/outputs and DLNs. In this paper we present the implementation of the FBIS control system, the integration of different hardware and software components and a summary on its performance during the latest beam commissioning phase to DTL4 Faraday Cup in 2023.

Poster TUPDP081 [2.284 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP081

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Received ※ 26 September 2023 — Accepted ※ 11 December 2023 — Issued ※ 16 December 2023

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TUPDP111

Software and Firmware-Logic Design for the PIP-II Machine Protection System Mode and Configuration Control at Fermilab

controls, interface, operation, linac

832

L.R. Carmichael, M.R. Austin, E.R. Harms, R. Neswold, A. Prosser, A. Warner, J.Y. Wu
Fermilab, Batavia, Illinois, USA

Funding: This manuscript has been authored by Fermi Research Alliance, LLC under Contract No. DE-AC02-07CH11359 with the U.S. Department of Energy, Office of Science, Office of High Energy Physics
The PIP-II Machine Protection System (MPS) requires a dedicated set of tools for configuration control and management of the machine modes and beam modes of the accelerator. The protection system reacts to signals from various elements of the machine according to rules established in a setup database filtered by the program Mode Controller. This is achieved in accordance with commands from the operator and governed by the firmware logic of the MPS. This paper describes the firmware logic, architecture, and implementation of the program mode controller in an EPICs based environment.

Poster TUPDP111 [2.313 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP111

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Received ※ 03 October 2023 — Revised ※ 09 October 2023 — Accepted ※ 04 December 2023 — Issued ※ 12 December 2023

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TUPDP123

SLAC ATCA Scope - Upgrading the EPICS Support Package

EPICS, software, controls, interface

873

D. Alnajjar, M.P. Donadio, K.H. Kim, R. Ruckman
SLAC, Menlo Park, California, USA

Funding: Work supported by US DOE contract DE-AC02-76SF00515
The SLAC ATCA Scope, a 4-channel dual scope, has an EPICS support package that runs on top of SLAC’s Common Platform software and firmware, and communicates with several high-performance systems in LCLS running on the 7-slot Advanced Telecommunications Computing Architecture (ATCA) crate. The software was completely refactored to improve the usability for IOC engineers. Once linked with an EPICS IOC, it initializes the scope hardware and instantiates the upper software stack providing a set of PVs to control the API and hardware, and to operate the oscilloscope. The exported PVs provide seamless means to configure triggers and obtain data acquisitions similar to a real oscilloscope. The ATCA scope probes are configured dynamically by the user to probe up to four inputs of the ATCA ADC daughter cards. The EPICS support package automatically manages available ATCA carrier board DRAM resources based on the number of samples requested by the user, allowing acquisitions of up to 8 GBytes per trigger. The user can also specify a desired sampling rate, and the ATCA Scope will estimate the nearest possible sampling rate using the current sampling frequency, and perform downsampling to try to match that rate. Adding the EPICS module to an IOC is simple and straightforward. The ATCA Scope support package works for all high-performance systems that have the scope common hardware implemented in its FPGAs. Generic interfaces developed in PyDM are also provided to the user to control the oscilloscope and enrich the user’s seamless overall experience.

Poster TUPDP123 [0.984 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-TUPDP123

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Received ※ 03 October 2023 — Accepted ※ 30 November 2023 — Issued ※ 08 December 2023

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WE1BCO01

VME2E: VME to Ethernet - Common Hardware Platform for legacy VME Module Upgrade

Ethernet, hardware, controls, real-time

949

J.P. Jamilkowski
Brookhaven National Laboratory (BNL), Electron-Ion Collider, Upton, New York, USA
Y. Tian
BNL, Upton, New York, USA

Funding: DOE Office of Science
VME architecture was developed in late 1970s. It has proved to be a rugged control system hardware platform for the last four decades. Today the VME hardware platform is facing four challenges from 1) backplane communication speed bottleneck; 2) computing power limits from centralized computing infrastructure; 3) obsolescence and cost issues to support a real-time operating system; 4) obsolescence issues of the legacy VME hardware. The next generation hardware platform such as ATCA and microTCA requires fundamental changes in hardware and software. It also needs large investment. For many legacy system upgrades, this approach is not applicable. We will discuss an open-source hardware platform, VME2E (VME to Ethernet), which allows the one-to-one replacement of legacy VME module without disassembling of the existing VME system. The VME2E has the VME form factor. It can be installed the existing VME chassis, but without use the VME backplane to communicate with the front-end computer and therefore solves the first three challenges listed above. The VME2E will only take advantage of two good benefits from a VME system: stable power supply which VME2E module will get from the backplane, and the cooling environment. The VME2E will have the most advanced 14nm Xilinx FPGA SOM with GigE for parallel computing and high speed communication. It has a high pin count (HPC) FPGA mezzanine connector (FMC) to benefit the IO daughter boards supply of the FMC ecosystem. The VME2E is designed as a low cost, open-source common platform for legacy VME upgrade.

Slides WE1BCO01 [1.141 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-WE1BCO01

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Received ※ 06 October 2023 — Revised ※ 09 October 2023 — Accepted ※ 19 November 2023 — Issued ※ 22 November 2023

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THMBCMO22

Towards Defining a Synchronization Standard Between Beamline Components and Synchrotron Accelerators

experiment, interface, hardware, synchrotron

1242

J.A. Avila-Abellan, X. Serra-Gallifa
ALBA-CELLS, Cerdanyola del Vallès, Spain
T.M. Cobb
DLS, Oxfordshire, United Kingdom
R. Hino
ESRF, Grenoble, France
O.H. Seeck
DESY, Hamburg, Germany
S. Zhang
SOLEIL, Gif-sur-Yvette, France

Funding: LEAPS-INNOV project has received funding from the European Union’s Horizon 2020 research and innovation program under Grant Agreement No 101004728
Standardization is a magic word in the electronics engineering jargon. Under its umbrella, it is generated the utopia of transparent integration with the rest of the parts with minimal extra effort for the software integration. But the experimental setup in a synchrotron beamline presents multiple challenges: it is highly dynamic and diverse. In the frame of LEAPS-INNOV project (*), the Task 3 of Work Package 5 aims to define a standard for synchronization in the beamline sample environment. Their partners (ALBA, DESY, DLS, ESRF and SOLEIL) have already reached a common vision of synchronization requirements. This paper first details the participants’ actual synchronization needs on their facilities. Next, the requirements foreseen for the future are outlined in terms of interfaces, time constraints and compatibility with timing systems. To conclude, we summarize the current state of the project: the hardware interfaces and the hardware platform definition. They both have been decided considering long-term availability, use of standard sub-components, and keeping the compromise between cost, development time, maintenance, reliability, flexibility and performance. This hardware architecture proposal meets the identified requirements. In the future, under the scope of LEAPS-INNOV, a demonstrator will be built, and we will work with the industry for its future commercialization.

Slides THMBCMO22 [1.592 MB]

Poster THMBCMO22 [0.760 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THMBCMO22

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Received ※ 06 October 2023 — Revised ※ 11 October 2023 — Accepted ※ 11 December 2023 — Issued ※ 19 December 2023

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THMBCMO26

FRIB Beam Power Ramp Process Checker at Chopper Monitor

diagnostics, target, controls, monitoring

1256

Z. Li, E. Bernal, J. Hartford, M. Ikegami
FRIB, East Lansing, Michigan, USA

Funding: Work supporting the U.S. Dept. of Energy Office of Science under Cooperative Agreement DE-SC0023633
Chopper in the low energy beam line is a key ele-ment to control beam power in FRIB. As appropriate functioning of chopper is critical for machine protec-tion for FRIB, an FPGA-based chopper monitoring system was developed to monitor the beam gated pulse at logic level, deflection high voltage level, and in-duced charge/discharge current levels, and shut off beam promptly at detection of a deviation outside tolerance. Once FRIB beam power reaches a certain level, a cold start beam ramp mode in which the pulse repetition frequency and pulse width are linearly ramped up becomes required to mitigate heat shock to the target at beam restart. Chopper also needs to gen-erate a notch in every machine cycle of 10 ms that is used for beam diagnostics. To overcome the challeng-es of monitoring such a ramping process and meeting the response time requirement of shutting off beam, two types of process checkers, namely, monitoring at the pulse level and monitoring at the machine cycle level, have been implemented. A pulse look ahead algorithm to calculate the expected range of frequency dips and rises was developed, and a simplified mathe-matical model suitable for multiple ramp stages was built to calculate expected time parameters of accumu-lated pulse on time within a given machine cycle. Both will be discussed in detail in this paper, followed by simulation results with FPGA test bench and actual instrument test results with the beam ramp process.

Slides THMBCMO26 [0.389 MB]

Poster THMBCMO26 [3.028 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THMBCMO26

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Received ※ 04 October 2023 — Revised ※ 10 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 24 October 2023

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THPDP002

The Micro-Services of Cern’s Critical Current Test Benches

controls, software, operation, power-supply

1295

C. Charrondière, A. Ballarino, C. Barth, J.F. Fleiter, P. Koziol, H. Reymond
CERN, Meyrin, Switzerland
O.Ø. Andreassen, T. Boutboul, S.C. Hopkins
European Organization for Nuclear Research (CERN), Geneva, Switzerland

In order to characterize the critical-current density of low temperature superconductors such as niobium¿titanium (NbTi) and niobium¿tin (Nb₃Sn) or high temperature superconductors such as magnesium-diboride MgB₂ or Rare-earth Barium Copper Oxide REBCO tapes, a wide range of custom instruments and interfaces are used. The critical current of a superconductor depends on temperature, magnetic field, current and strain, requiring high precision measurements in the nano Volt range, well-synchronized instrumentation, and the possibility to quickly adapt and replace instrumentation if needed. The micro-service based application presented in this paper allows operators to measure a variety of analog signals, such as the temperature of the cryostats and sample under test, magnetic field, current passing through the sample, voltage across the sample, pressure, helium level etc. During the run, the software protects the sample from quenching, controlling the current passed through it using high-speed field programmable gate array (FPGA) systems on Linux Real-Time (RT) based PCI eXtensions controllers (PXIe). The application records, analyzes and reports to the external Oracle database all parameters related to the test. In this paper, we describe the development of the micro-service based control system, how the interlocks and protection functionalities work, and how we had to develop a multi-windowed scalable acquisition application that could be adapted to the many changes occurring in the test facility.

Poster THPDP002 [6.988 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP002

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Received ※ 06 October 2023 — Revised ※ 10 October 2023 — Accepted ※ 13 October 2023 — Issued ※ 26 October 2023

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THPDP041

The RF Protection Interlock System Prototype Verification

LLRF, diagnostics, interface, software

1406

W. Cichalewski, P. Amrozik, G.W. Jabłoński, W. Jalmuzna, R. Kiełbik, K. Klys, R. Kotas, P. Marciniak, B. Pekoslawski, W. Tylman
TUL-DMCS, Łódż, Poland
B.E. Chase, E.R. Harms, N. Patel, P. Varghese
Fermilab, Batavia, Illinois, USA

The Radio Frequency Protection Interlock system plays vital role in the LLRF related/dependent accelerator sections Protection. It’s main role is to collect information from number different sensors and indicators around nearest cavities and cryomodule and provide instant RF signal termination in case of safety thresholds violation. This submission describes newly designed RFPI system tailored to the Proton Improvement Plan II (PIP-II) requirements. The proof of concept prototype of this system has been build. The paper includes also the CMTF environment evaluation tests results and findings as an input to the next full-scope prototype design.

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP041

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Received ※ 06 October 2023 — Revised ※ 26 October 2023 — Accepted ※ 08 December 2023 — Issued ※ 13 December 2023

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THPDP056

Consolidation of the Power Trigger Controllers of the LHC Beam Dumping System

controls, network, software, power-supply

1439

L. Strobino, N. Magnin, N. Voumard
European Organization for Nuclear Research (CERN), Geneva, Switzerland

The Power Trigger Controller (PTC) of the LHC Beam Dumping System (LBDS) is in charge of the control and supervision of the Power Trigger Units (PTU), which are used to trigger the conduction of the 50 High-Voltage Pulsed Generators (HVPG) of the LBDS kicker magnets. This card is integrated in an Industrial Control System (ICS) and has the double role of controlling the PTU operating mode and monitoring its status, and of supervising the LBDS triggering and re-triggering systems. As part of the LBDS consolidation during the LHC Long Shutdown 2 (LS2), a new PTC card was designed, based on a System-on-Chip (SoC) implemented in an FPGA. The FPGA contains an ARM Cortex-M3 softcore processor and all the required peripherals to communicate with onboard ADCs and DACs (3rd-party IPs or custom-made ones) as well as with an interchangeable fieldbus communication module, allowing the board to be integrated in various types of industrial control networks in view of future evolution. This new architecture is presented together with the advantages in terms of modularity and reusability for future projects.

Poster THPDP056 [3.146 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP056

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Received ※ 05 October 2023 — Accepted ※ 08 December 2023 — Issued ※ 15 December 2023

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THPDP080

Gateware and Software for ALS-U Instrumentation

controls, hardware, software, timing

1536

L.M. Russo, A. Amodio, M.J. Chin, W.E. Norum, K.S. Penney, G.J. Portmann, J.M. Weber
LBNL, Berkeley, California, USA

Funding: Work supported by the Director, Office of Science, Office of Basic Energy Sciences, of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231.
The Advanced Light Source Upgrade (ALS-U) is a diffraction-limited light source upgrade project under development at the Lawrence Berkeley National Laboratory. The Instrumentation team is responsible for developing hardware, gateware, embedded software and control system integration for diagnostics projects, including Beam Position Monitor (BPM), Fast Orbit Feedback (FOFB), High Speed Digitizer (HSD), Beam Current Monitor (BCM), as well as Fast Machine Protection System (FMPS) and Timing. This paper describes the gateware and software approach to these projects, its challenges, tests and integration plans for the novel accumulation and storage rings and transfer lines.

Poster THPDP080 [4.586 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP080

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Received ※ 04 October 2023 — Revised ※ 27 October 2023 — Accepted ※ 08 December 2023 — Issued ※ 15 December 2023

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THPDP087

LCLS-II Controls Software Architecture for the Wire Scan Diagnostics

controls, diagnostics, software, electron

1556

N. Balakrishnan, J.D. Bong, A.S. Fisher, B.T. Jacobson, L. Sapozhnikov
SLAC, Menlo Park, California, USA

Funding: This work was supported by Department of Energy, Office of Basic Energy Sciences, contract DE-AC02-76SF00515
The Super Conducting (SC) Linac Coherent Light Source II (LCLS-II) facility at SLAC is capable of delivering an electron beam at a fast rate of up to 1MHz. The high-rate necessitates the processing algorithms and data exchanges with other high-rate systems to be implemented with FPGA technology. For LCLS-II, SLAC has deployed a common platform solution (hardware, firmware, software) which is used by timing, machine protection and diagnostics systems. The wire scanner diagnostic system uses this solution to acquire beam synchronous time-stamped readings, of wire scanner position and beam loss during the scan, for each individual bunch. This paper explores the software architecture and control system integration for LCLS-II wire scanners using the common platform solution.

Poster THPDP087 [1.079 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP087

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Received ※ 06 October 2023 — Revised ※ 10 October 2023 — Accepted ※ 06 December 2023 — Issued ※ 09 December 2023

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THPDP088

ATCA-Based Beam Line Data Software for SLAC’s LCLS-II Timing System

software, EPICS, Linux, network

1560

D. Alnajjar, M.P. Donadio, K.H. Kim, M. Weaver
SLAC, Menlo Park, California, USA

Funding: Work supported by US DOE contract DE-AC02-76SF00515
Among the several acquisition services available with SLAC’s high beam rate accelerator, all of which are contemplated in the acquisition service EPICS support package, resides the new Advanced Telecommunications Computing Architecture (ATCA) Beam Line Data (BLD) service. BLD runs on top of SLAC’s common platform software and firmware, and communicates with several high-performance systems (i.e. MPS, BPM, LLRF, timing, etc.) in LCLS, running on a 7-slot ATCA crate. Once linked with an ATCA EPICS IOC and with the proper commands called in the IOC shell, it initializes the BLD FPGA logic and the upper software stack, and makes PVs available allowing the control of the BLD data acquisition rates, and the starting of the BLD data acquisition. This service permits the forwarding of acquired data to configured IP addresses and ports in the format of multicast network packets. Up to four BLD rates can be configured simultaneously, each accessible at its configured IP destination, and with a maximum rate of 1MHz. Users interested in acquiring any of the four BLD rates will need to register in the corresponding IP destination for receiving a copy of the multicast packet on their respective receiver software. BLD has allowed data to be transmitted over multicast packets for over a decade at SLAC, but always at a maximum rate of 120 Hz. The present work focuses on bringing this service to the high beam rate high-performance systems using ATCAs, allowing the reuse of many legacy in-house-developed client software infrastructures.

Poster THPDP088 [1.060 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP088

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Received ※ 03 October 2023 — Accepted ※ 06 December 2023 — Issued ※ 17 December 2023

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