JACoW is a publisher in Geneva, Switzerland that publishes the proceedings of accelerator conferences held around the world by an international collaboration of editors.
@inproceedings{gingold:icalepcs2023-mo4ao02,
author = {T. Gingold and G. Daniluk and M. Rizzi and J. Serrano and T. Włostowski},
title = {{HydRA: A System-on-Chip to Run Software in Radiation-Exposed Areas}},
% booktitle = {Proc. ICALEPCS'23},
booktitle = {Proc. 19th Int. Conf. Accel. Large Exp. Phys. Control Syst. (ICALEPCS'23)},
eventdate = {2023-10-09/2023-10-13},
pages = {217--221},
paper = {MO4AO02},
language = {english},
keywords = {radiation, software, electron, electronics, FPGA},
venue = {Cape Town, South Africa},
series = {International Conference on Accelerator and Large Experimental Physics Control Systems},
number = {19},
publisher = {JACoW Publishing, Geneva, Switzerland},
month = {02},
year = {2024},
issn = {2226-0358},
isbn = {978-3-95450-238-7},
doi = {10.18429/JACoW-ICALEPCS2023-MO4AO02},
url = {https://jacow.org/icalepcs2023/papers/mo4ao02.pdf},
abstract = {{In the context of the High-Luminosity LHC project at CERN, a platform has been developed to support groups needing to host electronics in radiation-exposed areas. This platform, called DI/OT, is based on a modular kit consisting of a System Board, Peripheral Boards and a radiation-tolerant power converter, all housed in a standard 3U crate. Groups customise their systems by designing Peripheral Boards and developing custom gateware and software for the System Board, featuring an IGLOO2 flash-based FPGA. It is compulsory for gateware designs to be radiation-tested in dedicated facilities before deployment. This process can be cumbersome and affects iteration time because access to radiation testing facilities is a scarce commodity. To make customisation more agile, we have developed a radiation-tolerant System-on-Chip (SoC), so that a single gateware design, extensively validated, can serve as a basis for different applications by just changing the software running in the processing unit of the SoC. HydRA (Hydra-like Resilient Architecture) features a triplicated RISC-V processor for safely running software in a radiation environment. This paper describes the overall context for the project, and then moves on to provide detailed explanations of all the design decisions for making HydRA radiation-tolerant, including the protection of programme and data memories. Test harnesses are also described, along with a summary of the test results so far. It concludes with ideas for further development and plans for deployment in the LHC. }},
}