<?xml version="1.0" encoding="UTF-8"?>
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    <record>
       <contributors>
          <authors>
             <author>Pavinato, S.</author>
             <author>Carroll, M.</author>
             <author>Gabourin, S.</author>
             <author>Gorzawski, A.A.</author>
             <author>Nordt, A.</author>
          </authors>
       </contributors>
       <titles>
          <title>
             The ESS Fast Beam Interlock System - Design, Deployment and Commissioning of the Normal Conducting Linac
          </title>
       </titles>
       <publisher>JACoW Publishing</publisher>
       <pub-location>Geneva, Switzerland</pub-location>
		 <isbn>2226-0358</isbn>
		 <isbn>978-3-95450-238-7</isbn>
		 <electronic-resource-num>10.18429/JACoW-ICALEPCS2023-TUPDP081</electronic-resource-num>
		 <language>English</language>
		 <pages>704-708</pages>
       <keywords>
          <keyword>MMI</keyword>
          <keyword>controls</keyword>
          <keyword>operation</keyword>
          <keyword>software</keyword>
          <keyword>FPGA</keyword>
       </keywords>
       <work-type>Contribution to a conference proceedings</work-type>
       <dates>
          <year>2024</year>
          <pub-dates>
             <date>2024-02</date>
          </pub-dates>
       </dates>
       <urls>
          <related-urls>
              <url>https://doi.org/10.18429/JACoW-ICALEPCS2023-TUPDP081</url>
              <url>https://jacow.org/icalepcs2023/papers/tupdp081.pdf</url>
          </related-urls>
       </urls>
       <abstract>
          The European Spallation Source (ESS) is a research facility based in Lund, Sweden. Its linac will have an high peak current of 62.5 mA and long pulse length of 2.86 ms with a repetition rate of 14 Hz. The Fast Beam Interlock System (FBIS), as core system of the Beam Interlock System at ESS, is a critical system for ensuring the safe and reliable operation of the ESS machine. It is a modular and distributed system. FBIS will collect data from all relevant accelerator and target systems through ~300 direct inputs and decides whether beam operation can start or must stop. The FBIS operates at high data speed and requires low-latency decision-making capability to avoid introducing delays and to ensure the protection of the accelerator. This is achieved through two main hardware blocks equipped with FPGA based boards: a mTCA ’Decision Logic Node’ (DLN), executing the protection logic and realizing interfaces to Higher-Level Safety, Timing and EPICS Control Systems. The second block, a cPCI form-factor ’Signal Condition Unit’ (SCU), implements the interface between FBIS inputs/outputs and DLNs. In this paper we present the implementation of the FBIS control system, the integration of different hardware and software components and a summary on its performance during the latest beam commissioning phase to DTL4 Faraday Cup in 2023. 
       </abstract>
    </record>
  </records>
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