Komiyama, M. Fujimaki, M. Fukunishi, N. Hamanaka, M. Kamoshida, A. Kaneko, K. Koyama, R. Nishimura, M. Uchiyama, A. Yamauchi, H. JACoW Publishing Geneva, Switzerland 2226-0358 978-3-95450-238-7 10.18429/JACoW-ICALEPCS2023-TUPDP050 English 645-649 controls EPICS operation FPGA experiment Contribution to a conference proceedings 2024 2024-02 https://doi.org/10.18429/JACoW-ICALEPCS2023-TUPDP050 https://jacow.org/icalepcs2023/papers/tupdp050.pdf We have been operating the beam interlock system (BIS) for machine protection of the RIKEN RI Beam Factory (RIBF) since 2006. It stops beams approximately 15 ms after receiving an alert signal from the accelerator and beam line components. We continue to operate BIS successfully; however, we are currently developing a successor system to stop a beam within 1 ms considering that the beam intensity of RIBF will continue to increase in the future. After comparing multiple systems, CompactRIO, a product by National Instruments, was selected for the successor system. Interlock logic for signal input/output is implemented on the field-programmable gate array (FPGA) because fast processing speed is required. On the other hand, signal condition setting and monitoring do not require the same speed as interlock logic. They are implemented on the RT-OS and controlled by using experimental physics and industrial control system (EPICS) by setting up an EPICS server on the RT-OS. As a first step in development, a prototype consisting of two stations that handle only digital alert signals was developed and installed in part of the RIBF in the summer of 2022 (224 input contacts). The signal response time of the prototype, measured with an oscilloscope, averaged 0.52 ms with both stations (the distance between two stations is approximately 75 m). Furthermore, by additionally installing a pull-up circuit at each signal input contact of the system, the system response time was successfully reduced to approximately 0.13 ms.