ICALEPCS2023 - List of Authors (Koprek, W.)

Paper	Title	Page
THPDP071	Application development on CPCI-S.0 Hardware at PSI	1508
	I.J. Johnson, R. Biffiger, D. Felici, W. Koprek, R. Rybaniec, B. Stef, G. Theidel PSI, Villigen PSI, Switzerland
	A Hardware and Software Toolbox is being created to accelerate the engineering of electronic components for large facility upgrades at the Paul Scherrer Institut. This Toolbox consists of modular hardware and Base Designs that follow the CPCI-S.0 concept. Our goal is to provide a starting foundation, tools, modules and libraries to simplify and accelerate developments. This contribution will focus on the Base Designs that provide advanced starting points for applications on MPSoC devices, AMD Zynq Ultrascale+. It is an environment containing both a ready-to-use system and functional building blocks. It features two main layers: one for the Processing System (PS) and one for the Programmable Logic (PL). The former is a collection of the software packages that run within an Operating System. The latter, lower layer consists of a seed Vivado project and an array of ready-to-use firmware modules. A set of device-tree-overlay scripts is also available to create high-level connections between PS and PL components.
	Poster THPDP071 [2.388 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP071
About •	Received ※ 06 October 2023 — Revised ※ 27 October 2023 — Accepted ※ 08 December 2023 — Issued ※ 09 December 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Application development on CPCI-S.0 Hardware at PSI

1508

I.J. Johnson, R. Biffiger, D. Felici, W. Koprek, R. Rybaniec, B. Stef, G. Theidel
PSI, Villigen PSI, Switzerland

A Hardware and Software Toolbox is being created to accelerate the engineering of electronic components for large facility upgrades at the Paul Scherrer Institut. This Toolbox consists of modular hardware and Base Designs that follow the CPCI-S.0 concept. Our goal is to provide a starting foundation, tools, modules and libraries to simplify and accelerate developments. This contribution will focus on the Base Designs that provide advanced starting points for applications on MPSoC devices, AMD Zynq Ultrascale+. It is an environment containing both a ready-to-use system and functional building blocks. It features two main layers: one for the Processing System (PS) and one for the Programmable Logic (PL). The former is a collection of the software packages that run within an Operating System. The latter, lower layer consists of a seed Vivado project and an array of ready-to-use firmware modules. A set of device-tree-overlay scripts is also available to create high-level connections between PS and PL components.

Poster THPDP071 [2.388 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-ICALEPCS2023-THPDP071

About •

Received ※ 06 October 2023 — Revised ※ 27 October 2023 — Accepted ※ 08 December 2023 — Issued ※ 09 December 2023

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)