FRIB, East Lansing, Michigan, USA
For more than a decade, the Eclipse-based Control System Studio has provided FRIB with a rich user interface to its EPICS-based control system. At FRIB, we use the Alarm Handler, BOY Display Manager, Scan Monitor/Editor, Channel Client, Save-and-Restore, and Data Browser to monitor and control various parts of the beamline. Our engineers have developed over 3000 displays using the BOY display manager mapping various segments and areas of the FRIB beamline. CS-Studio Phoebus is the latest next-generation upgrade to the Eclipse-based CS-Studio, which is based on the modern JavaFX-based graphics and aims toward providing existing functionalities and more. FRIB has already transitioned away from the old BEAST alarm servers to the new Kafka-based Phoebus alarm servers which have been monitoring thousands of our EPICS PVs with its robust monitoring and notifying capabilities. We faced certain challenges with conversion of FRIB’s thousands of displays and to address those we deployed scripts to help the bulk conversion of screens with automated mapping between BOY and Display Builder and also continually improved the Phoebus auto-conversion tool. This paper details the ongoing transition of FRIB from Eclipse-based CS-Studio to Phoebus and various adaptations and solutions that we used to ease this transition for our users. Moving to the new Phoebus-based services and client have provided us with an opportunity to rectify and improve on certain issues known to have existed with Eclipse-based CS-Studio and its services.
FRIB, East Lansing, Michigan, USA
Chopper in the low energy beam line is a key ele-ment to control beam power in FRIB. As appropriate functioning of chopper is critical for machine protec-tion for FRIB, an FPGA-based chopper monitoring system was developed to monitor the beam gated pulse at logic level, deflection high voltage level, and in-duced charge/discharge current levels, and shut off beam promptly at detection of a deviation outside tolerance. Once FRIB beam power reaches a certain level, a cold start beam ramp mode in which the pulse repetition frequency and pulse width are linearly ramped up becomes required to mitigate heat shock to the target at beam restart. Chopper also needs to gen-erate a notch in every machine cycle of 10 ms that is used for beam diagnostics. To overcome the challeng-es of monitoring such a ramping process and meeting the response time requirement of shutting off beam, two types of process checkers, namely, monitoring at the pulse level and monitoring at the machine cycle level, have been implemented. A pulse look ahead algorithm to calculate the expected range of frequency dips and rises was developed, and a simplified mathe-matical model suitable for multiple ramp stages was built to calculate expected time parameters of accumu-lated pulse on time within a given machine cycle. Both will be discussed in detail in this paper, followed by simulation results with FPGA test bench and actual instrument test results with the beam ramp process.