BNL, Upton, New York, USA
Osprey DCS LLC, Ocean City, USA
Brookhaven National Laboratory (BNL), Electron-Ion Collider, Upton, New York, USA
Preparations are underway to build the Electron Ion Collider (EIC) once Relativistic Heavy Ion Collider (RHIC) beam operations are end in 2025, providing an enhanced probe into the building blocks of nuclear physics for decades into the future. With commissioning of the new facility in mind, Accelerator Controls will require modernization in order to keep up with recent improvements in the field as well as to match the fundamental requirements of the accelerators that will be constructed. We will describe the status of the Controls System architecture that has been developed and prototyped for EIC, as well as plans for future work. Major influences on the requirements will be discussed, including EIC Common Platform applications as well as our expectation that we’ll need to support a hybrid environment covering both the proprietary RHIC Accelerator Device Object (ADO) environment as well as EPICS.
BNL, Upton, New York, USA
Modern timing distribution systems benefit from high configurability and the bidirectional transfer of timing data. The Electron Ion Collider (EIC) Common Hardware Platform (CHP) will integrate the functions of the existing RHIC Real Time Data Link (RTDL), Event Link, and Beam Sync Link, along with the Low-Level RF (LLRF) system Update Link (UL), into a common high speed serial link. One EIC CHP carrier board sup-ports up to eight external 8 Gbps high speed links via SFP+ modules, as well as up to six 8 Gbps high speed links to each of two daughterboards. A daughterboard will be designed for the purpose of timing data link distribution for use with the CHP. This daughterboard will have two high speed digital crosspoint switches and a Xilinx Artix Ultrascale+ FPGA onboard with GTY transceivers. One of these will be dedicated for a high-speed control and data link directly between the onboard FPGA and the carrier FPGA. The remaining GTY transceivers will be routed through the crosspoint switches. The daughterboard will support sixteen external SFP+ ports for timing distribution infrastructure with some ports dedicated for transmit only link fanout. The timing data link will support bidirectional data transfer including sending data or events from a downstream device back upstream. This flexibility will be achieved by routing the SFP+ ports through the crosspoint switches which allows the timing link datapaths to be forwarded directly through the daughterboard to the carrier and into the FPGA on the daughterboard in many different configurations.