JACoW is a publisher in Geneva, Switzerland that publishes the proceedings of accelerator conferences held around the world by an international collaboration of editors.
@unpublished{leonarski:icalepcs2023-thmbcmo38,
author = {F. Leonarski and M. Brückner and C. Lopez-Cuenca and A. Mozzanica and H.C. Stadler Kleeb and M. Wang},
title = {{Jungfraujoch: Data Acquisition and Real-Time Image Analysis System for Kilohertz X-Ray Pixel Array Detector}},
% booktitle = {Proc. ICALEPCS'23},
booktitle = {Proc. Int. Conf. Accel. Large Exp. Phys. Control Syst. (ICALEPCS'23)},
eventdate = {2023-10-09/2023-10-13},
language = {english},
intype = {presented at the},
series = {International Conference on Accelerator and Large Experimental Physics Control Systems},
number = {19},
venue = {Cape Town, South Africa},
publisher = {JACoW Publishing, Geneva, Switzerland},
month = {02},
year = {2024},
note = {presented at ICALEPCS'23 in Cape Town, South Africa, unpublished},
abstract = {{The Swiss Light Source (SLS) will shortly start an upgrade to become a 4th generation light source. The higher brilliance of the new source brings new science opportunities - one of them is improving time resolution for X-ray crystallography to a microsecond regime. However, fully utilizing the new machine will require increasing the frame rate of pixel array detectors and, thus, data volume. Nine-megapixel JUNGFRAU detector planned for SLS 2.0 beamlines will generate up to 36 GB/s raw data when operated at 2 kHz, which is very challenging for computing infrastructure. To operate this JUNGFRAU detector, PSI has developed a ’Jungfraujoch’ read-out system. The system can handle the complete data rate within a single server box for fast deployment at various beamlines. The system uses FPGA smart network interface cards for data acquisition, GPUs for on-the-fly image analysis (e.g., spot finding, radial integration), and high-end CPUs for image compression. In the presentation, I will show Jungfraujoch’s capabilities, experience from time-resolved macromolecular crystallography beamtimes, and technical details. I will highlight how FPGA design with high-level languages (C/C++) can help software developers design programmable logic quickly and how it can help in rapid verification. I will also present experiences working with a memory-coherent interconnect (OpenCAPI) to integrate FPGA boards into the server system and how it compares with a mainstream peripheral bus (PCI Express). }},
}